Flash memories have become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide. Each of the memory cells can be electrically charged by injecting electrons from the substrate through the oxide layer onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the source region or an erase gate during an erase operation. The data in flash memory cells are thus determined by the presence or absence of charges in the floating gates.
FIG. 1 illustrates two exemplary flash memory cells 2 and 20, wherein flash memory cells 2 and 20 share common source region 16 and common erase gate 18. Flash memory cell 2 includes a floating gate 4, a control gate 6 over and electrically insulated from floating gate 4, and a word-line node 10 over a channel 12 and on sidewalls of floating gate 4 and control gate 6. Word-line 10 controls the conduction of channel 12, which is between bit-line node 14 and source region 16. During a program operation, a voltage is applied between bit-line node 14 and source region 16, with, for example, a bit-line node voltage of about 0.4V and a source voltage of about 5V. Word-line 10 is applied with a voltage of 1.1V to turn on channel 12. Therefore, a current (hence electrons) flows between bit-line node 14 and source region 16. A high voltage, for example, about 10V, is applied on control gate 6, and thus the electrons are programmed into floating gate 4 under the influence of a high electrical field. During an erase operation, a high voltage, for example, 11V, is applied to erase gate 18. Word-line 10 is applied with a low voltage such as 0V, while source region 16, bit-line node 14 and control gate 6 are applied with a voltage of 0V. Electrons in floating gate 4 are thus driven into erase gate 18.
FIGS. 2A and 2B illustrate an intermediate stage in the manufacturing of flash memory cells. FIG. 2A illustrates a top view, while FIG. 2B illustrates a cross-sectional view along a plane crossing line A-A′ in FIG. 2A. At this stage, active regions 22 are covered with tunneling layer 23 and floating gate layer 26 (refer to FIG. 2B). Active regions 22 are surrounded by shallow trench isolation (STI) regions 24. Gate stacks 28 are located on floating gate layer 26, wherein each gate stack 28 will be a part of a resulting flash memory. Next, masks are formed, wherein edges 29 (refer to FIG. 2A) of the masks substantially overlap the edges of the respective gate stacks 28. An etch process is then performed to remove the portion of floating gate layer between gate stacks 28. Since the original floating gate layer has four legs, there are four floating gates formed, each separated from others.
With the increasing down-scaling of integrated circuits, the dimensions in the integrated circuits become increasingly smaller. In 90 nm technology, a distance D1 between edge 29 of the mask and the nearest edge of the STI regions can be as small as 300 Å. The precise alignment thus becomes increasingly important. For example, if a misalignment occurs, and the mask shifts to position 30, which is bordered using dashed lines, the floating gate at the upper left corner and the floating gate at the upper right corner will be shorted through a portion 32 of the floating gate layer, which is undesirably not removed due to the masking of the mask. As a result, the resulting memory fails. To make situation worse, STI regions 24 are typically rounded due to optical effects in the photo lithography. This may cause the tips (the portion of STI region 24 close to region 32) of STI regions 24 to recess from the desired position, and thus distance D1 is reduced. Accordingly, the likelihood of having shorted floating gates increases. New memory structures and formation methods are thus needed to solve the above-discussed problems.